The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased. This miniaturization of microelectronic devices continues to match or exceed the predictions of the International Technology Roadmap for Semiconductors. The minimum feature size is now approaching the critical edge of a typical polymer as used in conventional photoresist, and the line width roughness requirement for 32 nm node and beyond is already smaller than the polymer size. Although existing approaches have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.
In the prior art lithography processes, a conventional photoresist polymer is used. When this polymer is formed on the substrate, the molecules form in a random pattern and lack uniformity throughout the layer. After the photoresist is exposed and developed, there is a large line edge roughness (LER) that exists as a result of the random pattern of the photoresist molecules. This large LER causes the developed image to blur and reduces the resolution of the lithography and the subsequent etching process. This prevents the formation of the fine pattern required for the continued development of 32 nm and smaller devices.